This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-133168 filed on Apr. 27, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an automated wiring pattern layout method using CAD; a semiconductor integrated circuit, which is manufactured through this automated layout method; and storage media recorded with an automated layout program.
2. Description of the Related Art
Accompanying the increased large scale of circuits through progress in LSI technologies, the amount of circuit layout design and the mask design process have become immense. Therein, layout design is being performed through computer aided design (CAD), which is a logical design method capable of making effective use of a computer.
Accompanying the miniaturization of circuits in recent years, besides wiring resistance, the resistance of a VIA contact connecting differing layers of wiring to each other is an important element which must be considered when deciding chip performance. The mask for VIA contacts has a rectangular-shaped contact plane pattern with an aspect ratio (ratio of long edge to short edge) of nearly 1, and is the most miniature pattern in the various wiring masks. In addition, it is the region having a relatively small lithography process margin, where that region determines the accuracy of the lithography process. As one method of guaranteeing accuracy of such a post-exposure transferred pattern of such a minute shape, there is a method which shortens the wavelength of the light source used in photolithography; however shortening of the wavelength of the exposure light cannot always keep pace with device miniaturization, which increases every year.
Therefore, it has become important to have VIA design, which secures as much via contact cross-sectional area as the accuracy of the lithography can guarantee, and which uses current exposure apparatuses to the furthest extent possible.
In addition, with miniaturization processes of late, in order to compensate for the finished dimensions around the post-exposure processing VIA, layout pattern data correction is performed by conducting optical corrective processing called optical proximity correction (OPC). More specifically, as shown in FIG. 1A, with a CAD-based layout pattern, a VIA contact pattern 1301 is set at the end portion where two wiring patterns M1 and M2 intersect; however, if exposure is actually performed using a mask produced based on this layout pattern, as shown in FIG. 1B, the VIA contact pattern 1303 transferred onto the wafer is reduced. This reduction phenomenon is especially prominent in cases where the process margin for the lithography determining the mask process accuracy is small; thus the pattern transferred upon the wafer is remarkably reduced in comparison with the designed data. As a result, not only does the VIA resistance increase deteriorating the circuit performance, but breakage occurs due to weakened electromigration resistance.
According to an aspect of the present invention a wiring pattern layout method includes generating a first pattern with width W extending in a first direction and generating a second wiring pattern with width W extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end of the first wiring pattern. The method further includes generating an overlapping region by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and generating a rectangular-shaped VIA pattern at the overlapping region.
According to the first aspect of the present invention, a semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a first metal wiring on the first interlayer insulating layer. The first metal wiring has a width of W, extends in a first direction, and has a first end portion. The semiconductor device further includes a second interlayer insulating layer, which covers the first metal layer and first interlayer insulating layer. The semiconductor device furthermore includes a second metal wiring on the second interlayer insulating layer, and a VIA contact. The second metal extends in a direction perpendicular to the first metal wiring, and has an L-shaped bent region with a length of at least 2 W but no greater than 5 W overlapping the first end portion of the first metal wiring end. The VIA contact passes through the second interlayer insulating layer and connects the first end portion of the first metal wiring and the L-shaped bent region of the second metal wiring.
According to the first aspect of the present invention, a computer readable recording medium is recorded with a program for causing an automated layout device to operate. This program causes the automated layout device to generate a first wiring pattern with width W extending in a first direction, generate a second wiring pattern with width W extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. This program further causes it to generate an overlapping region by bending an end of either one of the first or the second wiring pattern at a right angle, extending to a length of at least 2 W but no greater than 5 W, and overlaying the first wiring pattern and the second wiring pattern, and generate at the overlapping region a rectangular-shaped VIA pattern having an aspect ratio of at least two but no greater than five.
According to a second aspect of the present invention, a wiring pattern optical correction method includes generating a first wiring pattern which extends in a first direction and generating a second wiring pattern. The second pattern extends diagonal to the first wiring pattern so that the end of the second wiring pattern overlaps the end of the first wiring pattern. The method further includes designating a parallelogram-shaped overlapping region, which has the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern as a center point, at the end portion where the first wiring pattern and second wiring pattern overlap. The method furthermore includes generating an expansion region, obtained by expanding in the same direction the respective outsides of the two edges along the first wiring pattern and also the respective outsides of the two edges along the diagonal second wiring pattern of the parallelogram-shaped overlapping region, generating a merge pattern by merging the second wiring pattern and the expansion region, and dividing the merge pattern into a plurality of regions along the same direction.
According to the second aspect of the present invention, a wiring pattern layout method includes generating a first wiring pattern with a width W extending in a first direction, generating a second wiring pattern with a width wider than width W of the first wiring pattern extending in a direction diagonal to the first wiring pattern so that end of the second wiring pattern overlaps the end of the first wiring pattern. The method further includes generating along the first wiring pattern, at the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern, a rectangular-shaped first VIA pattern having an aspect ratio of at least two so that the center point thereof matches the intersection.
According to a third aspect of the present invention, a wiring pattern optical correction method includes generating a first wiring pattern extending in a first direction, generating a second wiring pattern extending diagonal to the first wiring pattern so that the end of the second wiring pattern overlaps the end portion of the first wiring pattern. The method further includes designating at the end portion where the first wiring pattern and the second wiring pattern overlap a parallelogram-shaped overlapping region, which has the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern as a center point. The method furthermore includes generating at the intersection as a center a rectangular-shaped expansion region by expanding the rectangular-shaped overlapping region, generating a merge pattern by merging the second wiring pattern and the rectangular-shaped expansion region, and dividing the merge pattern into a plurality of regions along a single direction.
According to the third aspect of the present invention, a semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a first metal wiring on the first interlayer insulating layer. The first metal has a width of W, extends in a first direction, and has a first end portion. The semiconductor device further includes a second interlayer insulating layer, which is positioned covering the first metal layer and the first interlayer insulating layer. The semiconductor device furthermore includes a second metal wiring on the second interlayer insulating layer and a VIA contact. The second metal wiring extends in a diagonal direction forming a predetermined angle with the first metal wiring, has a second end positioned above first end of the first metal wiring, and has a width wider than width W of the first metal wiring. The VIA contact passes through the second interlayer insulating layer and connects the first end portion of the first metal wiring and second end portion of the second metal wiring.
According to the third aspect of the present invention, a computer readable recording medium is recorded with a program for causing an automated layout device to operate. This program causes the automated layout device to, generate a first wiring pattern with width W extending in a first direction, generate a second wiring pattern extending in a direction diagonal to the first wiring pattern so that the end thereof ends at the end portion of the first wiring pattern, detect the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern, and generate along the first wiring pattern with the extracted intersection as the center, a rectangular-shaped VIA pattern having an aspect ratio of at least two but no greater than five.
According to the third aspect of the present invention, a computer readable recording medium is recorded with a program for causing an optical correction device to operate. The program causes the optical correction device to read out a wiring layout including a first wiring pattern, which extends in a first direction and is generated by an automated layout device, a second wiring pattern and a rectangular-shaped VIA pattern. The second wiring pattern extends in a direction diagonal to the first wiring pattern and has an overlapping region where the end thereof and the end portion of the first wiring pattern overlap. The rectangular-shaped VIA pattern is positioned at the overlapping region. Thereafter the program causes the optical correction device to generate an expanded region by expanding the rectangular-shaped VIA pattern a predetermined rate with the center point thereof as a reference, generate a merge pattern by merging the expanded region and the second wiring pattern, and divide the merge pattern into a plurality of regions along a single direction.